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[VHDL-FPGA-Verilog] fir_filter

Description: 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
Platform: | Size: 3072 | Author: li | Hits:

[VHDL-FPGA-Verilog] gvhdl

Description: 初学ＶＨＤＬ有用的，了解后对复杂设计有很大帮助．-VHDL beginner useful understanding of the complexity of the design has been inspired by them.
Platform: | Size: 30720 | Author: 啊键 | Hits:

[VHDL-FPGA-Verilog] Verilog_example

Description: 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。 ，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
Platform: | Size: 1064960 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[Other] MUX

Description: 用CASE实现4选1数据选择器 很实用 运用VERILOG-Using CASE to achieve 4 election 1 Data Selector practical use Verilog
Platform: | Size: 1024 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] mux

Description: 多路选择器 verilog CPLD EPM1270 源代码-MUX source verilog CPLDEPM1270
Platform: | Size: 107520 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] mux

Description: 多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。-MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
Platform: | Size: 119808 | Author: 张应辉 | Hits:

[VHDL-FPGA-Verilog] Electronic-Design-Automation

Description: 用vhdl语句描述4位等值比较器，4选1多路选择器，8位奇偶校验电路功能-VHDL language used to describe the equivalent four comparators, 4 election more than one MUX, 8-bit parity circuit functions
Platform: | Size: 1024 | Author: 徐靖 | Hits:

[VHDL-FPGA-Verilog] mux21a

Description: 2选1多路选择器的VHDL完整描述，即可以直接综合出实现相应功能的逻辑电路及其功能器件。图6-1是此描述对应的逻辑图或者器件图-2 election more than one MUX complete description of the VHDL, which can be directly integrated to achieve the corresponding function logic devices and their functions. Figure 6-1 is the description of the corresponding device logic diagram or map
Platform: | Size: 3072 | Author: 刘阳 | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] mux21

Description: 一个比较简单的2选1多路选择器，初学者可以借以熟悉软件-A relatively easy one of the 2 election MUX, beginners can be so familiar with the software
Platform: | Size: 74752 | Author: 飞仔 | Hits:

[VHDL-FPGA-Verilog] mux

Description: Mulriplexer is implemented using VHDL.
Platform: | Size: 24576 | Author: nik | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: Very high speed integrated Hardware Description Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Description Language (VHDL)- is the IEEE, industry-standard hardware description language- rather than using language to describe graphics hardware, such as easy to modify the circuit easier to save- is particularly suited to the design of the circuit are: the complexity of combinational logic circuits, such as:- Decoder, encoder, plus or minus objects, MUX, address decoding
Platform: | Size: 1735680 | Author: sherry | Hits:

[Embeded-SCM Develop] Inpout32

Description: 32 bit inout mux for embedded design
Platform: | Size: 19456 | Author: kingtut | Hits:

[Windows Develop] directshow-MUX-DEMUX

Description: H.264解码器ffmpeg完整优化代码包括PC和WindowsMobile版本-ffmpeg WindowsMobile directshow mux implement
Platform: | Size: 361472 | Author: gan yong | Hits:

[VHDL-FPGA-Verilog] mux

Description: A Mux example written in VHDL.
Platform: | Size: 19456 | Author: Matheus | Hits:

[VHDL-FPGA-Verilog] mux

Description: VHDL realization of MultiPl
Platform: | Size: 164864 | Author: Sima | Hits:

[VHDL-FPGA-Verilog] mux

Description: vhdl code for multiplexer and detemines how multiplexer works
Platform: | Size: 1024 | Author: basheer | Hits:

[VHDL-FPGA-Verilog] 4x1_mux

Description: this a simple Verilog source code for 4X1 mux.-this is a simple Verilog source code for 4X1 mux.
Platform: | Size: 4096 | Author: firas | Hits:

[Other] mux

Description: In electronics, a multiplexer or mux is a device that performs multiplexing; it selects one of many analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. We will see VHDL code for a 2X1 multiplexer here
Platform: | Size: 2048 | Author: tariq | Hits:
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